FunCPU - Registers

The register file module has been completed as it is shown in the picture below. Please refer to architecture concept for an overview of registers and overall architecture.

It comprises the following registers:
  • RI (redex index) is implemented as a 74HC273 and used to store temporary the destination index value during function reduction. If a function cannot (yet) be called (because some of its arguments are not yet available. i.e. they are not constants), then reduction reverts to the target position defined by this index.
  • DI (destination index) is composed of two four bit registers using two 74HC161 chips. This holds the value of the destination register. This value can be stored temporary to and restored from RI.
  • SI (source index) is implemented in similar fashion, it stores the source index, it is selected to read the current symbol of source expression.
  • FI (function index) is also implemented similarly with two counters, it stores the function index, which is used to read/map the function definitions.
  • AC (argument counter) is implemented with a single 74HC161 chip. This acts as the argument counter to facilitate argument interpretation and handling. Note: this counter is slightly differently used as originally proposed to save parts and reduce complexity. This is also an up-counter, with the twist, that the binary value 1111 represents the "zero" value. Applying this encoding, the zero value can be detected by looking at the TC flag output.
  • V (value register) is implemented as a 74HC273. This register is used analogously to the accumulator of a traditional CPU (mainly accumulator machines). Calculated values are fetched to and from here between the memory and ALU.
  • S (state register) employs a 74HC175 to store processor state. This is a four bit value, 0000 represents initial state, whereas 1111 is the final state, when computation is finished and result is available. This register is refreshed, whenever a state transition is required, as governed by the micro-code.
  • SCZ - serves two purposes. The lower 3 bits are used to store the symbol classification value, the most significant bit is a flag, which tells whether argument count reached "logical" (recall the strange encoding) zero value. This register is usually refreshed upon restarting the micro-code sequence.

Please note that no register is fully or partially exposed to the programmer. The programming model does not make use of any registers directly. In fact, none of the registers can be manipulated or even accessed explicitly by the user program. All of these registers are, however, manipulated by the micro-sequencer, but it is hidden from the programmer.
Further observations:
  • No conventional PC (program counter) is employed.
  • No stack is present.
  • No nonventional processor state register or even flags (to denote zero, carry, overflow and so on) can be found here.

A small portion of the register module is dedicated to a 4 input multiplexer, which is introduced to select among four different address values. These are as follows:
  • SI - address determined by the source index. Generally used to fetch the next symbol of the expression being reduced.
  • DI - address determined by the destination index. This is selected, if the part of the reduced expression must be stored to the resulting expression.
  • FI - address as defined by the function index. This input is chosen when function definition is being unfolded.
  • Finally, SI + V', which is used when binding argument values in the course of unfolding function definition. Note: in such case SI register points to the next symbol in source expression. Assuming that the function has three arguments: SI-1, SI-2 and SI-3 represent argument 3, 2 and argument 1 respectively. Recall that argument numbers are encoded in two's complement form, therefore by simply adding SI and V' (modified V value holding the argument number in the binary form 1111 11xy) gives us the parameter value to be bounded to the argument in question. 
Register board being one of the main boards implements quite a fiew buses.

Bus 10 is utilized to drive data and tag classification signals from the RAM board.

Bus 11 transfers control signals defined by the micro-sequencer.

Bus 12 transfer further signals from the micro-sequencer.

Bus 13 supplies a 8 bit address signal to the RAM module.

Bus 14 provides the current CPU state, symbol class along with argument counter zero flag (as defined by the S and SCZ registers respectively).

Bus 15 supplies two ALU input sources, the SI and the V register.

Bus 16 receives the 8 bit ALU result, which is fed to the address multiplexer.

Finally, bus 17 is used to pass some control signals together with argument counter and power supply lines to ALU.